Digital integrated circuit chips are composed of many millions of gates that make up various functional components on a chip such as flip-flops, multiplexers, logic circuits, etc. A given chip design may have thousands of flip-flops scattered throughout the chip. A manufacturer may test these flip-flops by shifting in a string of binary ones and zeros through scan chains of flip-flops. The data that is captured at the end of these scan chains is used to validate performance of the chip.
The methodology used to scan test a chip is time-consuming and may require a significant amount of test data in order to validate the performance of the entire chip. A complete scan test of the entire chip is usually performed.
When a portion of an integrated circuit design is modified, resulting in a revised prototype, only a subset of the design is affected. Unfortunately, however, all scan chains must be tested. This results in considerable test time and increased costs of manufacture.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.